`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    18:36:13 10/28/2014 
// Design Name: 
// Module Name:    Main 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Main(
	input clk, reset, 
	input rx,
	output tx
//	output [7:0] salida_rx,
//	output rx_done
    );
	 
//wire tick, tx_done, rx_done;
//wire [7:0] d_out_rx;
//wire [7:0] d_in_tx;
//wire [7:0] r_data_rx;
//wire [7:0] w_data_tx;
//wire full_tx, empty_rx, empty_tx;
//wire rd_rx,wr_tx, tx_fifo_not_empty;
wire [7:0] datos;
wire rx_done_tx_start;

BaudRateGenerator brg ( .clock(clk),.reset(reset), .tick(tick));

Rx rx_dmo (.data(rx), .tick(tick), .Data_Out(datos), .rx_done(rx_done_tx_start)); //Este es el verdadero

Tx tx_dmo (.d_in(datos), .tx_start(rx_done_tx_start), .tick(tick), .tx(tx), .tx_done());

//assign salida_rx = datos;
//assign rx_done = rx_done_tx_start;

//Fifo #(.B(8),.W(2)) Fifo_Rx(.clk(clk), .reset(reset), .rd(rd_rx), .wr(rx_done), .w_data(d_out_rx), .full(),
 //.empty(empty_rx), .r_data(r_data_rx));

//Fifo Fifo_Tx(.clk(clk), .reset(reset), .rd(tx_done), .wr(wr_tx), .w_data(w_data_tx), .full(full_tx),
 //.empty(empty_tx), .r_data(d_in_tx));

//UnidorCableadorUART tuto(.r_data(r_data_rx), .rx_empty(empty_rx), .tx_full(full_tx), .rd(rd_rx),
 //.wr(wr_tx), .w_data(w_data_tx));
 
//assign tx_fifo_not_empty = ~ empty_tx;


endmodule
